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datasheet 932SQL450 revision b 03/06/15 1 ?2015 integrated device technology, inc. low-power ck420bq derivative for pcie common clock architectures 932SQL450 general description the 932SQL450 is a low power version of the ck420bq synthesizer for intel-based server platforms. it has 85-ohm lp-hcsl outputs allowing for direct connection to 85-ohm transmission lines. the 932SQL450 is driven with a 25mhz crystal for maximum performanc e. it generates cpu outputs of 100mhz. this device has a ?low-drift? non-spread sas/src pll for use in systems that need to communicate across pcie domains. recommended application low power ck420bq w/zout=85ohms or pcie common clocked systems (cc) key specifications ? cpu, src, ns_src and ns_sas cycle-cycle jitter <50ps ? output to output skew <50ps ? phase jitter: pcie gen2 <2.5ps rms ? phase jitter: pcie gen3 <0.6ps rms ? phase jitter: qpi <0.3ps rms ? phase jitter: ns-sas <1.3ps rms using long period phase jitter method features/benefits ? integrated 85 ohm differential terminations; saves 48 resistors and 82mm 2 area ? lp-hcsl output drivers; 40% typical power savings over 932sq420 ? 0.5% down spread capable on cpu, src and pci outputs; reduce emi ? additional down spread amounts selectable via smbus; maximal system flexibility ? 64-pin tssop and vfqfpn packages; smallest board footprint output features ? 4 - low-power hcsl-compatible (lp-hcsl) cpu outputs ? 2 - lp-hcsl ns_sas outputs ? 2 - lp-hcsl ns_src outputs ? 3 - lp-hcsl src outputs ? 1 - lp-hcsl dot96 output ? 1 - 3.3v 48m output ? 5 - 3.3v pci outputs ? 1 - 3.3v 14.318m output pin configurations smbclk 1 64 smbdat gnd14 2 63 vddcpu avdd14 3 62 cpu3_z85t vdd14 4 61 cpu3_z85c v ref14_2x/test_sellv 5 60 cpu2_z85t gnd14 6 59 cpu2_z85c gndxtal 7 58 gndcpu x1_25 8 57 vddcpu x2_25 9 56 cpu1_z85t vddxtal10 55cpu1_z85c gndpci 11 54 cpu0_z85t vddpci 12 53 cpu0_z85c pci4_2x 13 52 gndns pci3_2x 14 51 avdd_ns_sas pci2_2x 15 50 ns_sas1_z85t pci1_2x 16 49 ns_sas1_z85c pci0_2x 17 48 ns_sas0_z85t gndpci 18 47 ns_sas0_z85c vddpci 19 46 gndns vdd48 20 45 vddns 48m_2x 21 44 ns_src1_z85t gnd48 22 43 ns_src1_z85c gnd96 23 42 ns_src0_z85t dot96_z85t 24 41 ns_src0_z85c dot96_z85c 25 40 nc avdd96 26 39 gndsrc test_mode 27 38 avdd_src ckpwrgd#/pd 28 37 vddsrc vddsrc 29 36 src2_z85t src0_z85t 30 35 src2_z85c src0_z85c 31 34 src1_z85t gndsrc 32 33 src1_z85c 64-tssop note: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldown 932SQL450 vddxtal x2_25 x1_25 gndxtal gnd14 vref14_2x/test_sellv vdd14 avdd14 gnd14 smbclk smbdat vddcpu cpu3_z85t cpu3_z85c cpu2_z85t cpu2_z85c 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gndpci 1 48 gndcpu vddpci 2 47 vddcpu pci4_2x 3 46 cpu1_z85t pci3_2x 4 45 cpu1_z85c pci2_2x 5 44 cpu0_z85t pci1_2x 6 43 cpu0_z85c pci0_2x 7 42 gndns gndpci 841avdd_ns_sas vddpci 9 40 ns_sas1_z85t vdd48 10 39 ns_sas1_z85c 48m_2x 11 38 ns_sas0_z85t gnd48 12 37 ns_sas0_z85c gnd96 13 36 gndns dot96_z85t 14 35 vddns dot96_z85c 15 34 ns_src1_z85t avdd96 16 33 ns_src1_z85c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 test_mode ckpwrgd#/pd vddsrc src0_z85t src0_z85c gndsrc src1_z85c src1_z85t src2_z85c src2_z85t vddsrc avdd_src gndsrc nc ns_src0_z85c ns_src0_z85t note: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldown 64-pin vfqfpn 932SQL450 epad = pin 65
low-power ck420bq derivative for pcie common clock architectures 2 revi sion b 03/06/15 932SQL450 datasheet 64tssop pin descriptions pin # pin name type description 1 smbclk in clock pin of smbus circuitry, 5v tolerant 2 gnd14 pwr ground pin for 14mhz output and logic. 3 avdd14 pwr analog power pin for 14mhz pll 4 vdd14 pwr power pin for 14mhz output and logic 5 vref14_2x/test_sellv i/o 14.318 mhz reference clock capable of driving 2 loads/ test_sel latched input to enable test mode. the test_sel input is a low threshold input. see the electrical tables and the test clarification table. this pin has a weak (~120kohm) internal pull down. 6 gnd14 pwr ground pin for 14mhz output and logic. 7 gndxtal pwr ground pin for crystal osc illator. 8 x1_25 in crystal input, nominally 25.00mhz. 9 x2_25 out crystal output, nominally 25.00mhz. 10 vddxtal pwr 3.3v power for the crystal oscillator. 11 gndpci pwr ground pin for pci outputs and logic. 12 vddpci pwr 3.3v power for the pci outputs and logic 13 pci4_2x out 3.3v pci clock output capable of driving two loads. 14 pci3_2x out 3.3v pci clock output capable of driving two loads. 15 pci2_2x out 3.3v pci clock output capable of driving two loads. 16 pci1_2x out 3.3v pci clock output capable of driving two loads. 17 pci0_2x out 3.3v pci clock output capable of driving two loads. 18 gndpci pwr ground pin for pci outputs and logic. 19 vddpci pwr 3.3v power for the pci outputs and logic 20 vdd48 pwr 3.3v power for the 48mhz output and logic 21 48m_2x out 3.3v 48mhz output capable of driving 2 loads. 22 gnd48 pwr ground pin for 48mhz output and logic. 23 gnd96 pwr ground pin for dot96 output and logic. 24 dot96_z85t out true clock of low-power push-pull differential 96mhz output. internally terminated to drive 85ohm transmission lines with no external components. 25 dot96_z85c out complementary clock of low-power push-pull differential 96mhz output. internally terminated to drive 85ohm transmission lines with no external components. 26 avdd96 pwr 3.3v power for the 48/96mhz pll and the 96mhz output and logic 27 test_mode in test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 28 ckpwrgd#/pd in ckpwrgd# is an active low input used to sample latched inputs and allow the device to power up. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks and plls are stopped. 29 vddsrc pwr 3.3v power for the src outputs and logic 30 src0_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 31 src0_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 32 gndsrc pwr ground pin for src outputs and logic. 33 src1_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 34 src1_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 35 src2_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 36 src2_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 37 vddsrc pwr 3.3v power for the src outputs and logic 38 avdd_src pwr 3.3v power for the src pll analog circuits 39 gndsrc pwr ground pin for src outputs and logic. 40 nc n/a no connection.
revision b 03/06/15 3 low-power ck420bq de rivative for pcie commo n clock architectures 932SQL450 datasheet 64tssop pin descriptions (cont.) pin # pin name type description 41 ns_src0_z85c out complementary clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 42 ns_src0_z85t out true clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 43 ns_src1_z85c out complementary clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 44 ns_src1_z85t out true clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 45 vddns pwr 3.3v power for the non-spr eading differential outputs outputs and logic 46 gndns pwr gr ound pin for non-spreading differential outputs and logic. 47 ns_sas0_z85c out complementary clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 48 ns_sas0_z85t out true clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 49 ns_sas1_z85c out complementary clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 50 ns_sas1_z85t out true clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 51 avdd_ns_sas pwr 3.3v power for the non-spreading sas/src pll analog circuits. 52 gndns pwr gr ound pin for non-spreading differential outputs and logic. 53 cpu0_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 54 cpu0_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 55 cpu1_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 56 cpu1_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 57 vddcpu pwr 3.3v power for the cpu outputs and logic 58 gndcpu pwr gr ound pin for cpu outputs and logic. 59 cpu2_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 60 cpu2_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 61 cpu3_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 62 cpu3_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 63 vddcpu pwr 3.3v power for the cpu outputs and logic 64 smbdat i/o data pin of smbus circuitry, 5v tolerant
low-power ck420bq derivative for pcie common clock architectures 4 revi sion b 03/06/15 932SQL450 datasheet 64vfqfpn pin descriptions pin # pin name type description 1 gndpci pwr ground pin for pci outputs and logic. 2 vddpci pwr 3.3v power for the pci outputs and logic 3 pci4_2x out 3.3v pci clock output capable of drivin g two loads. 4 pci3_2x out 3.3v pci clock output capable of driving two loads. 5 pci2_2x out 3.3v pci clock output capable of driving two loads. 6 pci1_2x out 3.3v pci clock output capable of driving two loads. 7 pci0_2x out 3.3v pci clock output capable of drivin g two loads. 8 gndpci pwr ground pin for pci outputs and logic. 9 vddpci pwr 3.3v power for the pci outputs and logic 10 vdd48 pwr 3.3v power for the 48mhz output and logic 11 48m_2x out 3.3v 48mhz output capable of drivin g 2 loads. 12 gnd48 pwr ground pin for 48mhz output and logic. 13 gnd96 pwr ground pin for dot96 output and logic. 14 dot96_z85t out true clock of low-power push-pull differential 96mhz output. internally terminated to drive 85ohm transmission lines with no external components. 15 dot96_z85c out complementary clock of low-power push-pull differential 96mhz output. internally terminated to drive 85ohm transmission lines with no external components. 16 avdd96 pwr 3.3v power for the 48/96mhz pll and the 96mhz output and logic 17 test_mode in test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 18 ckpwrgd#/pd in ckpwrgd# is an active low input used to sample latched inputs and allow the device to power up. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks and plls are sto pped. 19 vddsrc pwr 3.3v power for the src outputs and logic 20 src0_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 21 src0_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 22 gndsrc pwr ground pin for src outputs and logic. 23 src1_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 24 src1_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 25 src2_z85c out complementary clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 26 src2_z85t out true clock of low-power push-pull differential src output. internally terminated to drive 85ohm transmission lines with no external components. 27 vddsrc pwr 3.3v power for the src outputs and logic 28 avdd_src pwr 3.3v power for the src pll analo g circuits 29 gndsrc pwr ground pin for src outputs and logic. 30 nc n/a no connection. 31 ns_src0_z85c out complementary clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 32 ns_src0_z85t out true clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 33 ns_src1_z85c out complementary clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 34 ns_src1_z85t out true clock of low-power push-pull differential non-spreading src output. internally terminated to drive 85ohm transmission lines with no external components. 35 vddns pwr 3.3v power for the non-spreading differential outputs outputs and logic 36 gndns pwr ground pin for non-spreadin g differential outputs and lo g ic. 38 ns_sas0_z85t out true clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components.
revision b 03/06/15 5 low-power ck420bq de rivative for pcie commo n clock architectures 932SQL450 datasheet 64vfqfpn pin descriptions (cont.) pin # pin name type description 39 ns_sas1_z85c out complementary clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 40 ns_sas1_z85t out true clock of low-power push-pull differential non-spreading sas output. internally terminated to drive 85ohm transmission lines with no external components. 41 avdd_ns_sas pwr 3.3v power for the non-spreading sas/src pll analog circuits. 42 gndns pwr ground pin for non-spreading differential outputs and logic. 43 cpu0_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 44 cpu0_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 45 cpu1_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 46 cpu1_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 47 vddcpu pwr 3.3v power for the cpu outputs and logic 48 gndcpu pwr ground pin for cpu outputs and lo g ic. 49 cpu2_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 50 cpu2_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 51 cpu3_z85c out complementary clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 52 cpu3_z85t out true clock of low-power push-pull differential cpu output. internally terminated to drive 85ohm transmission lines with no external components. 53 vddcpu pwr 3.3v power for the cpu outputs and logic 54 smbdat i/o data pin of smbus circuitry, 5v tolerant 55 smbclk in clock pin of smbus circuitry, 5v tolerant 56 gnd14 pwr ground pin for 14mhz output and lo g ic. 57 avdd14 pwr analog power pin for 14mhz pll 58 vdd14 pwr power pin for 14mhz output and logic 59 vref14_2x/test_sellv i/o 14.318 mhz reference clock capable of driving 2 loads/ test_sel latched input to enable test mode. the test_sel input is a low threshold input. see the electrical tables and the test clarification table. this pin has a weak (~120kohm) internal pull down. 60 gnd14 pwr ground pin for 14mhz output and logic. 61 gndxtal pwr ground pin for crystal oscillator. 62 x1_25 in crystal input, nominally 25.00mhz. 63 x2_25 out crystal output, nominally 25.00mhz. 64 vddxtal pwr 3.3v power for the crystal oscillator. 65 epad gnd epad should be co nnected to ground.
low-power ck420bq derivative for pcie common clock architectures 6 revi sion b 03/06/15 932SQL450 datasheet block diagram cpu_src_pci pll (ss) low drift non- ss pll <500ps ltj non-ss pll 14.31818mhz non-ss pll logic smbclk smbdat ckpwrgd#/pd test_mode test_sel /3 ref14_2x /2 48m_2x x1_25 x2_25 cpu(3:0)_z85 src(2:0)_z85 pci(4:0)_2x ns_sas(1:0)_z85 ns_src(1:0)_z85 dot96_z85
revision b 03/06/15 7 low-power ck420bq de rivative for pcie commo n clock architectures 932SQL450 datasheet power supply and test loads alternate terminations power group pin numbers vdd gnd vdd gnd 57 56 3 2 14mhz pll analog 58 60 4 6 ref14m output and logic 64 61 10 7 25mhz xtal 2, 9 1, 8 12, 19 11, 18 pci outputs and logic 10 12 20 22 48mhz output and logic 16 13 26 23 96mhz pll analog, output and logic 19, 27 22 29, 37 32 src outputs and logic 28 29 38 39 src pll analog 35 36 45 46 non-spreading differential outputs & logic 41 42 51 52 ns-sas/src pll analog 47, 53 48 57,63 58 cpu outputs and logic vfqfpn description tssop low-power differential output (w/integrated rs) test load 2pf 10 inches zo = 85 ? 2pf rs=27 ? cl=5pf 20 inches zo = 50 ? single-ended output test load alternate termination for driving 100 ? transmission lines 2pf zo = 100 ? 2pf rs=7 ? rs=7 ? rs=16 ? zo = 50 ? cl=5pf rs=16 ? zo = 50 ? cl=5pf alternate termination for driving 2 50 ? loads
low-power ck420bq derivative for pcie common clock architectures 8 revi sion b 03/06/15 932SQL450 datasheet functionality and cpu sas frequency tables 932SQL450 functionality cpu src pci ref ns_sas ns_src dot96 usb 100 100 33.33 14.318 100.00 96.00 48.00 mhz spread spectrum control functionality ss_enable (b1b0) cpu, src & pci 0off 1-0.50% 932SQL450 power down functionality ckpwrgd#/pd differential outputs single- ended outputs single- ended outputs w/latch 1 low/low low low 1 0 1. single-ended outputs with a latch will be hi-z until the first application of ckpwrgd#. running line byte6 bit2 fs2 byte6 bit1 fs1 byte6 bit0 fs0 cpu speed (mhz) src (mhz) pci (mhz) 0 0 0 0 97.00 97.00 32.33 1 0 0 1 98.00 98.00 32.67 2 0 1 0 99.00 99.00 33.00 3 0 1 1 100.00 100.00 33.33 default for 100mhz 4 1 0 0 101.00 101.00 33.67 5 1 0 1 102.00 102.00 34.00 6 1 1 0 103.00 103.00 34.33 7 1 1 1 104.00 104.00 34.67 cpu/src/pci margining table line byte5 bit3 fs3 byte5 bit2 fs2 byte5 bit1 fs1 byte5 bit0 fs0 ns_xxx (mhz) 0 0 00082.5 1 0 00185.0 2 0 01087.5 3 0 01190.0 4 0 10092.5 5 0 10195.0 6 0 11097.5 7 0111 100.0 8 1 0 0 0 102.5 9 1 0 0 1 105.0 10 1 0 1 0 107.5 11 1 0 1 1 110.0 12 1 1 0 0 112.5 13 1 1 0 1 115.0 14 1 1 1 0 117.5 15 1 1 1 1 120.0 ns_sas margining table note: operation at other than the default entry is not guaranteed. these values are for margining purposes only.
revision b 03/06/15 9 low-power ck420bq de rivative for pcie commo n clock architectures 932SQL450 datasheet clock ac tolerances clock periods?outputs with spread spectrum disabled clock periods?outputs with spread spectrum enabled cpu, src ns_sas, ns_src pci dot96 48mhz ref 100 100 100 100 100 100 ppm 50 50 500 250 350 1000 ps -0.50% 0.00% -0.50% 0 0.00% 0.00% % ppm tolerance c y cle to c y cle jitter spread 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average ma x +c2c jitter absper max cpu 100.000 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 src, ns_sas, ns_src 100.000 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 pci 33.333 29.49700 29.99700 30.00000 30.00300 30.50300 ns 1,2 dot96 96.000 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2 48mhz 48.000 20.48125 20.83125 20.83333 20.83542 21.18542 ns 1,2 ref 14.318 69.78429 69.83429 69.84128 69.84826 69.89826 ns 1,2 notes measurement window units ssc off center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average ma x +c2c jitter absper max cpu 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 pci 33.25 29.49718 29.99718 30.07218 30.07519 30.07820 30.15320 30.65320 ns 1,2 src 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy specifications are guaranteed with the assumption that the ref output is tuned to exactly 14.31818mhz. measurement window units ssc on center freq. mhz notes
low-power ck420bq derivative for pcie common clock architectures 10 revision b 03/06/15 932SQL450 datasheet general smbus serial interface information for 932SQL450 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) id t (slave/receiver) tstart bit slave address d2 (h) wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit read address write address d3 (h) d2 (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address d2 (h) wr write ack beginning byte = n ack rt repeat start slave address d3 (h) rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
revision b 03/06/15 11 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet note: pin numbers refer to tssop smbus table: output enable register pin # name control function t yp e 0 1 defaul t bit 7 dot96 enable output enable rw disable-low/low enable 1 bit 6 ns_sas1 e nable output enable rw disable-low/low enable 1 bit 5 ns_sas0 e nable output enable rw disable-low/low enable 1 bit 4 ns_src1 enable output enable rw disable-low/low enable 1 bit 3 ns_src0 enable output enable rw disable-low/low enable 1 bit 2 src2 enable output enable rw disable-low/low enable 1 bit 1 src1 enable output enable rw disable-low/low enable 1 bit 0 src0 enable output enable rw disable-low/low enable 1 smbus table: output enable register pin # name control function t yp e 0 1 defaul t bit 7 ref14_3x enable output enable rw disable-low enable 1 bit 6 0 bit 5 0 bit 4 cpu3 output enable rw disable-low/low enable 1 bit 3 cpu2 output enable rw disable-low/low enable 1 bit 2 cpu1 output enable rw disable-low/low enable 1 bit 1 cpu0 output enable rw disable-low/low enable 1 bit 0 spread spectrum enable spread off/on rw spread off spread on 0 smbus table: output enable register pin # name control function t yp e 0 1 defaul t bit 7 0 bit 6 0 bit 5 pci4 enable output enable rw disable-low enable 1 bit 4 pci3 enable output enable rw disable-low enable 1 bit 3 pci2 enable output enable rw disable-low enable 1 bit 2 pci1 enable output enable rw disable-low enable 1 bit 1 pci0 enable output enable rw disable-low enable 1 bit 0 48mhz enable output enable rw disable-low enable 1 smbus table: differential amplitude control pin # name control function t yp e 0 1 defaul t bit 7 cpu amplitude 1 rw 00 = 700mv 01 = 800mv 0 bit 6 cpu amplitude 0 rw 10 = 900mv 11 = 1000mv 1 bit 5 src amplitude 1 rw 00 = 700mv 01 = 800mv 0 bit 4 src amplitude 0 rw 10 = 900mv 11 = 1000mv 1 bit 3 dot96 amplitude 1 rw 00 = 700mv 01 = 800mv 0 bit 2 dot96 amplitude 0 rw 10 = 900mv 11 = 1000mv 1 bit 1 ns-sas/src amplitude 1 rw 00 = 700mv 01 = 800mv 0 bit 0 ns-sas/src amplitude 0 rw 10 = 900mv 11 = 1000mv 1 smbus table: spread amount register pin # name control function t yp e 0 1 defaul t bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 ss amount[1] rw 00= -0.2% 10= -0.4% 1 bit 0 ss amount[0] rw 01= -0.3% 11= -0.5% 1 reserved reserved 30/31 b y te 1 62/61 14 reserved reserved reserved 16 54/53 b y te 2 b y te 3 b y te 4 17 21 b y te 0 24/25 48/47 44/43 50/49 60/59 15 36/35 34/33 5 13 cpu/src/ pci 56/55 42/41 reserved reserved cpu vhigh src vhigh dot96 vhigh ns-sas/src vhigh reserved reserved spread amount (note b1b0 must be set to '1') reserved
low-power ck420bq derivative for pcie common clock architectures 12 revision b 03/06/15 932SQL450 datasheet smbus table: ns_sas/ns_src frequency margining table pin # name control function t yp e 0 1 defaul t bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 fs3 freq. sel 3 rw 0 bit 2 fs2 freq. sel 2 rw 1 bit 1 fs1 freq. sel 1 rw 1 bit 0 fs0 freq. sel 0 rw 1 smbus table: test mode and cpu/src/pci frequency select register pin # name control function t yp e 0 1 defaul t bit 7 test mode test mode type rw hi-z ref/n 0 bit 6 test select select test mode rw disable enable 0 bit 5 0 bit 4 1 bit 3 0 bit 2 fs2 freq. sel 2 rw 0 bit 1 fs1 freq. sel 1 rw 1 bit 0 fs0 freq. sel 0 rw 1 note: internal pull up on 100m_133m# pin will result in default cpu frequency of 100 mhz. smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 1 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: byte count register pin # name control function t yp e 0 1 defaul t bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 0 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 1 smbus table: device id register pin # name control function t yp e 0 1 defaul t bit 7 did7 r --0 bit 6 did6 r --1 bit 5 did5 r --0 bit 4 did4 r --0 bit 3 did3 r --0 bit 2 did2 r --1 bit 1 did1 r --0 bit 0 did0 r --1 - - - - - see cpu/src/pci frequency select table reserved - 1 for b rev 0001 for ics/idt - b y te 9 - - b y te 5 - b y te 6 - - - reserved revision id (1h forb rev) see ns_sas/ns_src frequency table. reserved byte 7 - - - - b y te 8 - - - - - - reserved - - - - reserved - reserved device id (45 hex) byte count programming b(7:0) writing to this register will configure how many bytes will be read back, default is a bytes. (0 to 9 vendor id reserved
revision b 03/06/15 13 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 932SQL450. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaran teed only over the recommended operating temperature range. electrical characteristi cs?current consumption ac electrical characteristics? differential lp-hcsl outputs (cpu, src, ns_sas, ns_src, dot96) parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 case temperature tc 110 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. ta = t com ; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active cpu@100mhz, see test loads. 233 265 ma powerdown current i dd3.3pdz 610ma ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes duty cycle t dc measured differentially, pll mode 45 49.9 55 % 1 skew, output to output t sk3src across all src outputs, v t = 50% 40 50 ps 1 skew, output to output t sk3cpu across all cpu outputs, v t = 50% 19 50 ps 1 cpu, src, ns_sas outputs 15 50 ps 1,3 dot96 output 16 250 ps 1,3 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 zo=85 ? (differential impedance). 3 measured from differential waveform jitter, cycle to cycle t jcyc-cyc
low-power ck420bq derivative for pcie common clock architectures 14 revision b 03/06/15 932SQL450 datasheet electrical characteristics?in put/supply/common parameters ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial r ange 0 70 c input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs. v in = 0 v; inputs with internal pull- up resistors v in = vdd; inputs with internal pull- down resistors -200 200 ua input frequency f i 25.00 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c ou t output pin capacitance 5 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.4 1.8 ms 1,2 ss modulation frequency f modi n allowable frequency (triangular modulation) 30 31.5 33 khz 1 tdrive_pd# t drvpd differential output enable after pd# de-assertion 98 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v smbus input high voltage v ihsmb 2.1 v ddsmb v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are >200 mv input current capacitance
revision b 03/06/15 15 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet dc electrical characteristics? differential lp-hcsl outputs (cpu, src, ns_sas, ns_src, dot96) electrical characteristics?48mhz t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate dv/dt scope avera g in g on 1.5 2.9 4 v/ns 1,2,3 slew rate matching ? dv/dt slew rate matching, scope averaging on 520 % 1,2,4 voltage high vhigh 660 774 850 voltage low vlow -150 83 150 max voltage vmax 918 1150 7 min voltage vmin -300 -3 7 vswin g vswin g scope avera g in g off 300 1359 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 250 432 550 mv 1,5 crossing voltage (var) ? -vcross scope averaging off 14 140 mv 1,6 2 measured from differential waveform 7 includes overshoot and undershoot. 8 measured from single-ended waveform 9 measured with scope averaging off, using statistics function. variation is difference betw een min and max. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv wi ndow centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. statistical measurement on single- ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope mv 1 guaranteed by design and characterization, not 100% tested in production. z o =85 ? (differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window around differential 0v. t a = 0 - 70c; supply voltage v dd/ v dda = 3.3 v +/-5%, parameter symbol conditions min typ max units notes output impedance r dsp v o = v d d *(0.5) 12 21.7 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v clock high time t hi gh 1.5v 8.094 10.036 ns 1 clock low time t low 1.5v 7.694 9.836 ns 1 edge rate t slewr/f_usb rising/falling edge rate 1 2.3 v/ns 1,2 duty cycle d t1 v t = 1.5 v 45 50.4 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 see "power supply and test loads" page for termination circuits 1 guaranteed by design and characterization, not 100% tested in production. 2 measured between 0.8v and 2.0v
low-power ck420bq derivative for pcie common clock architectures 16 revision b 03/06/15 932SQL450 datasheet electrical characteristics? phase jitter parameters electrical characteristics?pci t a = 0 - 70c; supply voltage v dd/ v dda = 3.3 v +/-5%, parameter symbol conditions min typ max indust. limit units notes t jphpcieg1 pcie gen 1 35 39 86 ps (p-p) 1,2,3, 6 pcie gen 2 lo band 10khz < f < 1.5mhz 1.52 1.84 3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.19 2.42 3.1 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.51 0.59 1 ps (rms) 1,2,4, 6 qpi & smi (100mhz, 4.8gb/s, 6.4gb/s 12ui) 0.25 0.37 0.5 ps (rms) 1,5,7 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.18 0.23 0.3 ps (rms) 1,5,7 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.15 0.19 0.2 ps (rms) 1,5,7 t jphsas12g sas 12g 1.15 1.27 1.3 ps (rms) 1,5,8 1 guaranteed by design and characterization, not 100% tested in production. 6 applied to src outputs 7 applies to cpu outputs 8 applies to ns_sas, ns_src outputs, spread off 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. 5 calculated from intel-supplied clock jitter tool v 1.6.6 phase jitter t jphpcieg2 t jphqpi_smi 2 see http://www.pcisi g .com for complete specs t a = 0 - 70c; supply voltage v dd/ v dda = 3.3 v +/-5%, parameter symbol conditions min typ max units notes output impedance r dsp v o = v d d *(0.5) 12 22 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v clock high time t hi gh 1.5v 12 ns 1 clock low time t low 1.5v 12 ns 1 edge rate t slewr/f rising/falling edge rate 1 1.7 4 v/ns 1,2 duty cycle d t1 v t = 1.5 v 45 50.4 55 % 1 group skew t skew v t = 1.5 v 197 500 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 45.52 500 ps 1 see "power supply and test loads" page for termination circuits 1 guaranteed by design and characterization, not 100% tested in production. 2 measured between 0.8v and 2.0v
revision b 03/06/15 17 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet electrical characteristics?ref14m test clarification table t a = 0 - 70c; supply voltage v dd/ v dda = 3.3 v +/-5%, parameter symbol conditions min typ max units notes output impedance r dsp v o = v d d *(0.5) 12 21.7 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v clock high time t hi gh 1.5v 27.5 ns 1 clock low time t low 1.5v 27.5 ns 1 edge rate t slewr/f rising/falling edge rate 1 1.9 4 v/ns 1,2 duty cycle d t1 v t = 1.5 v 45 50.1 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 42 1000 ps 1 see "power supply and test loads" page for termination circuits 1 guaranteed by design and characterization, not 100% tested in production. 2 measured between 0.8v and 2.0v comments test_sel hw pin test_mod e hw pin test entry bit b6b6 ref/n or hi-z b6b7 output 0 x 0 x normal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n b6b6: 1= enter test mode, default = 0 (normal operation) b6b7: 1= ref/n, default = 0 (hi-z) hw sw power-up w/ test_sel = 1 ( >0.7v ) to enter test mode. cycle power to disable test mode. if test_sel hw pin is 0 during power-up, test mode can be selected through b6b6. if test mode is selected by b6b6, then b6b7 is used to select hi-z or ref/n fs_b/test_mode pin is not used. cycle power to disable test mode.
low-power ck420bq derivative for pcie common clock architectures 18 revision b 03/06/15 932SQL450 datasheet recommended crystal char acteristics ( 3225 package) marking diagrams notes: 1. ?l? denotes pb-fre e, rohs compliant. 2. ?lot? denotes the lot number. 3. ?yyww? denotes the last two digits and week the part was assembled. 4. ?coo? denotes the country of origin. 5. ?b? denotes the device revision designator. 6. bottom marking (tssop only): country of origin. parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stab ility, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature ran g e (industrial) -40~85 c 2 equivalent series resistance (esr) 50 ? max 1 shunt capacitance (c o )7pf max1 load capacitance (c l )8pf max1 drive level 0.3 mw max 1 aging per year 5 ppm max 1 notes: 1. fox electronics 603-25-150 or equivalent 2. for i-temp, contact fox electronics at foxonline.com 64tssop ics lot yyww 932SQL450bgl 64vfqfpn ics 932SQL450bl lot coo yyww
revision b 03/06/15 19 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet package outline and package dimensions (64-pin tssop) index area 1 2 48 d e1 e seating plane a1 a a2 e - c - b aaa c ? c l *for reference only. controlling dimensions in mm. millimeters inches* symbol minmaxminmax a ? 1.20 ? .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 0.32 0.41 b0.170.27.007.011 c 0.09 0.20 .0035 .008 d 16.90 17.10 .665 .673 e 8.10 basic 0.319 basic e1 6.00 6.20 .236 .244 e 0.50 basic 0.020 basic aaa ? 0.10 ? .004 l 0.450.75.018.030 a0 ? 8 ? 0 ? 8 ? 64
low-power ck420bq derivative for pcie common clock architectures 20 revision b 03/06/15 932SQL450 datasheet package outline and package dimensions (64-pin vfqfpn)
revision b 03/06/15 21 low-power ck420bq derivative for pcie commo n clock architectures 932SQL450 datasheet package outline and package dimensions (64-pin vfqfpn), cont.
low-power ck420bq derivative for pcie common clock architectures 22 revision b 03/06/15 932SQL450 datasheet ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (will not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 932SQL450bglf tubes 64-pin tssop 0 to +70 c 932SQL450bglft tape and reel 64-pin tssop 0 to +70 c 932SQL450bklf tray 64-pin vfqfpn 0 to +70 c 932SQL450bklft tape and reel 64-pin vfqfpn 0 to +70 c rev. issue date who description page # a 3/5/2014 rdw 1. updated electrical table format and data to final. 2. updated test_sel pin description and test clarification table to indicate that this input is a low threshold input. 3. updated test loads and added alternate terminations diagrams. 4. updated block diagram to latest format and updated pin names to match the pinout. 5. updated front page text to latest format 6. move to final. various b 3/6/2015 rdw 1. corrected typo in powerdown current max limit. max limit changed from 9ma to 10ma. 13
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